This invention especially relates to writing to and reading from storage, such as that used in communications and computer systems; and more particularly, the invention relates to reading from and writing to storage, including, but not limited to memory devices, using acknowledged phases of sets of data.
The communications industry is rapidly changing to adjust to emerging technologies and ever increasing customer demand. This customer demand for new applications and increased performance of existing applications is driving communications network and system providers to employ networks and systems having greater speed and capacity (e.g., greater bandwidth). In trying to achieve these goals, a common approach taken by many communications providers is to use packet switching technology. Increasingly, public and private communications networks are being built and expanded using various packet technologies, such as Internet Protocol (IP).
A network device, such as a switch or router, typically receives, processes, and forwards or discards a packet. For example, a enqueuing component of such a device receives a stream of various sized packets which are accumulated in an input buffer. Each packet is analyzed, and an appropriate amount of memory space is allocated to store the packet. The packet is stored in memory, while certain attributes (e.g., destination information and other information typically derived from a packet header or other source) are maintained in separate memory. A memory interface typically dictates the amount of information written into memory each clock cycle, and typically a packet, especially a large packet, is written to memory over multiple clock cycles. Once the entire packet is written into memory, the packet becomes eligible for processing, and an indicator of the packet is typically placed in an appropriate destination queue for being serviced according to some scheduling algorithm.
The dequeue machine operates in parallel, running an scheduling algorithm to determine which packet should be read from the memory into an output buffer. Once the entire data is read into the output buffer, the packet can be forwarded to a next component or system, and the buffer space it occupied is freed for other packets.
As packets are received at higher rates, then these operations must also be performed at higher rates. The nature of the system and of the large fast memories, which exist in today""s market, introduces a problem of ordering in memory accessing. The order of the actual memory accesses is very hard to predict due to various reasons, including the varying nature of traffic and the burstiness behavior of both read and write side, especially as the number of read and write accesses varies.
The characteristics of the external memories imply that for achieving maximum efficiency, most of the memory accesses have to be reordered to avoid conflicts. This means that the order in which they were issued by the enqueue machine to the memory interface is not necessarily the order in which they are actually written to the memory. Switches from read to write and vice versa, should be as infrequent as possible, because switching also causes a penalty in the number of memory accesses. This means that the memory interface should attempt executing as many writes as it can before switching to read and vice versa, and this fact further weakens the correlation between the order of issuing a memory access, and the order of execution. As a result of these and other factors, complex processing must be performed to determine when an entire packet data is actually written to memory and is thus eligible for being enqueued to the appropriate target queue. Similar processing must be performed to determine when the entire packet""s data is read, and the memory space can be freed.
New methods and apparatus are needed for efficiently determining when the data of an entire packet is read from or written to storage.
Methods and apparatus are disclosed for reading from and writing to storage, including, but not limited to memory devices, using acknowledged phases of sets of data. In one embodiment, a phase indication is maintained. A first value of the phase indication is associated with a first plurality of storage requests, and a second value of the phase indication is associated with a second plurality of storage requests. The first and second pluralities of storage requests are forwarded to a storage control component. A first acknowledgement that the first plurality of storage requests have been manipulated is received. In one embodiment, the plurality of storage requests include a write request. In one embodiment, the plurality of storage requests include a read request.